The increasing tightness of the chip structures leads to more and more increasing noise problems while determining the state of a Symmetrical Random Access Memory Cell (SRAM) according to the state of the art or while writing such a cell. Furthermore negative side effects on neighboring cells occur.
The standard 6T (six transistor) SRAM cell suffers for example from instability during read operations. This has a significant impact on the yield of modern microprocessor fabrication since modern microprocessors are provided with large memories on the microprocessor chip. The issue is expected to become even more severe in future semiconductor technology generations.
With the symmetrical 6T cell, instability is likely to occur when the cell's dedicated wordline is active for read operation, thus establishing conductive paths between the two complementary bit-lines and the cell-internal nodes respectively.
Known solution approaches are cells with bigger devices or more devices, especially 8T or 10T cell approaches. But because of the needed massive usage of cells the area consumption of a cell is essential. So such approaches have an inevitable drawback.
There was an effort to improve the stability by selectively increasing the drive strength of the p-channel pull-up transistors, but this degrades the write performance in an intolerable way.
Another approach is to increase the supply voltage used together with 6T SRAMs to improve the stability by raising the supply voltage as known in the sate of the art. The major drawback of such an approach lies therein that due to the energy dissipation problem the higher voltage can only be realized within the range of the SRAM cells, not however in the logic surrounding and controlling the memory cells. Therefore such solutions have to operate with a least two different supply voltages on the same chip. The larger the voltage raise for the cells is selected, the more difficult it will be to write the cells.
Further a second supply voltage must be generated and distributed via extra structures on the chip. This represents a substantial negative cost factor. Another difficulty lies therein that decreasing supply voltages are intended to be used, whereby occurring disturbing fluctuations in the supply voltage levels could hardly be prevented.
European patent application EP1505607 A1 proposes an asymmetric static random access memory device, which is described to reduce bit-line leakage, wherein the memory comprises a column having opposing bit lines, asymmetric memory cells spanning the opposing bit lines in alternating orientations, and a sense amplifier. The sense amplifier includes sensing circuitry configured to sense values stored in the cells and switching circuitry configured to apply signals to the sensing circuitry as a function of the orientations. A major drawback on this technique is the need of a very technology-specific sense amplifier.
The article by Navid Azizi, Farid N. Najm, Andreas Moshovos, titled “Low-Leakage Asymmetric-Cell SRAM”, from IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003, p. 701-715 describes asymmetric SRAM cells that reduce leakage power in caches while maintaining low access latency. A major drawback on this technique is the need of a complex sense amplifier, in combination with dummy bit-lines, to produce read times which are on par with conventional symmetric cells.
Therefore a need exists to avoid the extensive and therefore expensive increase of use of space on the chip in order to overcome the noise problems.